Recently, each of many electronic makers receives a semiconductor device and a device model obtained by modeling the semiconductor device from a semiconductor vendor and performs circuit design and transmission simulation of a printed circuit board to be mounted on an electronic device. Moreover, though a spice model and an IBIS (Input/output Buffer Information Specification) model are publicly known as device models, the latter IBIS model is mainstream.
Therefore, most electronic makers respectively perform circuit design and transmission simulation of a printed circuit board using a semiconductor device according to an IBIS model received from a semiconductor vendor. However, when checking by a semiconductor vendor is not strict, an IBIS model in which many errors are included in description syntax or various parameters is supplied to an electronic maker. Therefore, a problem occurs that a trouble occurs in a printed circuit board concerned serving as an actual model even if there is no problem in circuit design and transmission simulation. Therefore, unit and a method for effectively solving the above problem have been earnestly desired so far.
The spice model serving as a device model is used to show circuit operations to a designer by simulating the circuit operations by a computer without forming an actual circuit on a printed circuit board and show a process parameter or configuration of a circuit. Therefore, when supplying the spice model to an electronic maker, the process parameter and configuration of a circuit included in the company secret of a semiconductor vendor is opened to the public and thereby, a state undesirable for the semiconductor vendor occurs.
However, the IBIS model shows input/output characteristics of a semiconductor device, in which the package characteristic, V/I (voltage/current) characteristic, and switching characteristic of the semiconductor device are described in the form of a table.
Therefore, when supplying the IBIS model to an electronic maker, advantages are obtained that the process parameter and configuration of a circuit included in the company secret of a semiconductor vendor are not opened to the public and moreover, the information necessary for circuit design and transmission simulation is obtained by an electronic maker side. Therefore, the IBIS model is conventionally mainstream as a device model to be supplied to an electronic maker from a semiconductor vendor.
FIG. 29 and FIG. 30 are illustrations showing an IBIS file F0 showing the IBIS model. As shown in FIG. 29 and FIG. 30, the IBIS file F0 is constituted of header data and part data. Moreover, the part data includes pin model data.
The header data includes the data for the file name, date, and version and the like about the IBIS file F0. Specifically, in the case of the header data shown in FIG. 29, the version of an IBIS is described in [IBIS Ver] and comment characters are described in [Comment Char]. The file name of the IBIS file F0 is described in [File Name] and the revision level of the IBIS file F0 is described in [File Rev]. The creation date of the IBIS file F0 is described in [Date].
The creation source of the IBIS file F0 is described in [Source] and notes about the IBIS file F0 are described in [Notes]. The information about disclaimer of right is described in [Disclaimer] and the information about copyright is described in [Copyright].
Moreover, in the case of the part data shown in FIG. 29, the formal type name of the semiconductor device concerned is described in [Component] and the information about the manufacturer of the semiconductor device concerned is described in [Manufacturer]. Values such as the RLC (resistance value, inductance, and capacitance) of the default of the package section of a semiconductor device are described in [Package] and the information about relating of an I/O model with an external pin and a signal name is described in [Pin].
Moreover, in the case of the pin model data, the definition of a pin model is described in [Model]. The definition starts with [Model] and is described up to the next [Model] (not shown) or [End] (refer to FIG. 30). The information about the model type of a pin is described in [Model_type] and the information about electrical polarities (Non-Inverting or Inverting) is described in [Polarity].
The information for designating active high or active low (Active-High or Active-Low) is described in [Enable]. The upper limit of an input low-level voltage is described in [Vinl] and the lower limit of an input high-level voltage is described in [Vinh]. A measurement reference voltage value for measuring the propagation delay and output switching time of a semiconductor device is described in [Vmeas].
The circuit configuration information (capacitance value, resistance value, and voltage value) for measuring the propagation delay and output switching time of a semiconductor device is described in [Cref], [Rref], and [Vref]. The capacitance value of a silicon die is described in [C_comp]. The operating temperature of a semiconductor device is described in [Temperature Range]. The supply voltage value for measuring [Pullup] and [Power clamp] (refer to FIG. 30) to be described later is described in [Voltage range].
The V/I (voltage/current) characteristic of a pulled-down output buffer is described in [Pulldown] shown in FIG. 30 and the V/I (voltage/current) characteristic of a pulled-up output buffer is described in [Pullup]. The V/I characteristic of a grounded clamp diode is described in [GND_clamp]. The V/I characteristic of a clamp diode connected to a power supply is described in [Power_clamp].
The rise time (dV/dt_r) and fall time (dV/dt_f) of an output pin voltage are described in [Ramp]. dV is equal to 20 to 80% of the amplitude of an output pin voltage dt denotes the time consumed for 20 to 80%. [End] is described in the end of the IBIS file concerned.
A semiconductor vendor converts the spice model to the IBIS model by using a conversion tool and supplies the IBIS file F0 corresponding to the IBIS model to an electronic maker. The electronic maker executes circuit design and transmission simulation by using the IBIS file F0.
As described above, an IBIS model including trouble information may be conventionally supplied to an electronic maker due to erroneous setting of or insufficient checking by a conversion tool when converting a spice model to an IBIS model.
In this case, because an electronic maker executes circuit design and transmission simulation by using an IBIS model including trouble information, a critical problem occurs that a trouble occurs in a printed circuit board serving as an actual model.
In this case, to solve the above problem, it is considered that the electronic maker checks the trouble of the IBIS model and corrects the trouble information. However, an advanced user skill well-versed in an IBIS model is requested for the checking and correction of the trouble information.
Therefore, in the case of an electronic maker insufficient in the number of talents having the user skill, it is substantially difficult to perform checking and correction of trouble information and the maker cannot find a trouble until a trouble occurs in a printed circuit board serving as an actual model and then it cannot be helped to take a post-action that the maker requests a semiconductor vendor to specify and correct a defective section of an IBIS model. Therefore, it is conventionally difficult to completely correspond to the needs of designing a printed circuit board in a short period.